Embodiments of the present invention relate to semiconductor devices, and more particularly to interfacing semiconductor devices with system-level interconnect structures.
Today's semiconductor devices feature ever-increasing processing capabilities in smaller packages, and continue to operate at higher frequencies. Higher processing speeds and reduced size can lead to various issues, including power and temperature-related issues. Accordingly, many processors are now being manufactured that include multiple cores in a single package, and even multiple cores on a single die. Such processors can perform high-level processing tasks at lower temperatures, reducing heat dissipation. Furthermore, greater amounts of processing can be done at lower frequencies using multiple cores.
However, integrating multiple cores in a single package such as a processor socket can lead to various issues. One such issue is the effect of multiple cores on electrical performance. Specifically, multiple cores, each of which includes digital logic circuitry as well as analog input/output (I/O) interface circuitry, create a significant electrical load on an interconnect medium through which the processor socket is coupled to a system. For example, many computer systems include a system bus, often referred to as a front side bus (FSB), that is a multi-drop bus used to couple the processor to other system components, such as a memory controller hub (MCH), system memory, and other system components. To avoid negative electrical performance issues, the FSB may be controlled to run at a lower frequency, affecting performance. Such a lower bus frequency can significantly impact performance for dual core or other multiple core devices, as bandwidth demand can increase in proportion to the number of cores.
Some dual core processor designs connect cores together in a package in a manner similar to routing between multiple processor sockets in a multiple processor system. However, such a design degrades electrical performance of the FSB. In particular, the package trace length is significantly increased and capacitance is also increased, which can significantly limit I/O frequency. Other manners of connecting cores can cause significant design efforts that increase complexity and affect a base core design.